Design of Low Power Carry Look-Ahead Adder Using Single Phase Clocked Quasi-Static Adiabatic Logic
نویسندگان
چکیده
Efficiency of adiabatic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. Lesser be the losses more energy efficient would be the circuit. In this paper, a new approach i.e., Complementary Energy Path Adiabatic Logic (CEPAL), is presented to minimize power dissipation in quasi static energy recovery logic (QSERL). It optimizes circuit, by avoiding non-adiabatic losses completely by replacing the diodes with MOSFETs. MOSFET gates are controlled by power clocks and this is implemented in Carry Look-Ahead Adder structure. Firstly, the performance attributes of CEPAL Carry Look-Ahead Adder are compared against the conventional static CMOS logic counterpart to identify its adiabatic power advantage. The analyses are carried out using the industry standard Tanner EDA design environment using 250nm technology libraries. The results prove that CEPAL adiabatic Carry LookAhead Adder results in 56.05% of power savings over static CMOS.
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